1. Field of the Invention.
The present invention relates to a semiconductor integrated circuit device and, in particular, to an integrated circuit device for use in an emitter coupled logic (ECL) circuit.
2. Description of the Prior Art
Emitter coupled logic (ECL) generally refers to a family of bipolar integrated circuits, often used in digital applications. ECL circuits are characterized by short propagation delay times, which are typically on the order of 1 ns. The switching speed of ECL circuits is achieved by maintaining the active devices in these circuits outside of their saturation region, and by limiting the size of changes in voltage levels associated with switching between logical states. By keeping the changes in voltages small, the delays associated with charging or discharging load capacitances or parasitic capacitances are reduced. A concise description of emitter coupled logic circuits can be found in the textbook H. Haznedar, Digital Microelectronics 266-91 (1991 ).
As an example of prior art ECL circuits, FIG. 1 shows a circuit diagram for a three input OR/NOR gate. This ECL circuit consists of two stages: (1) a differential logic stage which includes a current switch; and (2) an output emitter-follower stage acting as an output buffer circuit.
The inputs to the differential logic stage consist of three NPN transistors Q.sub.1-1, Q.sub.1-2 and Q.sub.1-3, which are connected in parallel. Together these input transistors make up one branch of the differential logic stage. Input signals IN.sub.A, IN.sub.B and IN.sub.C are applied to the bases of the three input transistors, respectively. The collectors of the input transistors are grounded in common through load resistor R.sub.1, and the emitters of the three transistors are connected in common to a constant current source I.sub.cs. The other branch of the differential logic stage consists of an NPN transistor Q.sub.2 which has a reference potential V.sub.BB1 applied to its base. Transistor Q.sub.2 has its collector grounded through load resistance R.sub.2 and its emitter connected to the constant current source I.sub.cs. Thus, the emitters of the transistors on either side of the differential logic stage are coupled. When the voltage of one or more of the three input signals IN.sub.A IN.sub.B or IN.sub.C is higher than the reference potential V.sub.BB1, the associated input transistor switches on and current begins to flow through the load resistance R.sub.1 on the left side branch of the differential logic stage. As current begins flowing through the left side of the differential logic stage, the common emitter voltage begins to rise until transistor Q.sub.2 switches off. In this state no current flows through the right side branch load resistance R.sub.2. Because at least one transistor on the left side branch is switched on and because Q.sub.2 is switched off, the potential at the collectors of the left side branch falls to a low "L" level and the potential at the collector of Q.sub.2 increases to a high "H" level.
For most applications, an emitter-follower circuit is connected as an output stage to each of the two branches of the differential logic stage. The base of the emitter-follower NPN junction is connected to the junction point between the load resistor (R.sub.1 or R.sub.2) and the collector(s) of the transistor(s). Accordingly, when current is flowing through the left side of the differential logic stage, the right side output Z of the emitter-follower stage is set to the "H" level and the left side output Z of the emitter-follower stage is set to the "L" level. On the other hand, when the voltage levels of all three input signals are lower than the reference potential V.sub.BB1, a current I.sub.cs flows through the right side branch so that the output Z is set to the "L" level and the left side output Z is set to the "H" level. In the manner described above, it is possible to obtain a logical output Z that is indicative of the three input OR operation: Z=A+B+C.
For the circuit shown in FIG. 1, when Q.sub.2 is switched off so that the right branch potential increases from the "L" level to the "H" level, the Z output switches at a fast speed because the Z output is driven by emitter-follower transistor Q.sub.4. In contrast, when Q.sub.2 is switched on and the Z output of the right side emitter-follower stage decreases from the "H" level to the "L" level, either the switching operation will be slow, or excessive levels of power will be consumed for high speed switching. It is difficult to achieve high speed operation while maintaining power consumption at an optimum level--for prior art ECL circuits, circuit optimization involves a trade-off between high speed and low power operation. This is because the output load is discharged by the current I.sub.EF that flows from the constant current source through an equivalent resistance R.sub.E (not shown). To change the output Z of the emitter-follower stage from the "H" level to the "L" level at high speed, a large current I.sub.EF (or a small equivalent resistance R.sub.E) is required, so that the power consumption increases. This power is consumed throughout steady state operation; that is, power is consumed even when the ECL gate output is not being switched. To reduce this power loss, either the current I.sub.EF must be reduced or the resistance R.sub.E must be increased. However, reducing the current flow in this way causes the switching time to increase to an unacceptable level.
As an illustration of this problem, FIG. 3 shows the results of a simulation in which an output of the ECL inverter circuit shown in FIG. 2 (similar to the circuit shown in FIG. 1) is used to drive different output loads (C.sub.L =0.04 pF, 0.5 pF, and 1.0 pF) under the condition that I.sub.EF =235 .mu.A. FIG. 3 indicates that the time required to switch from an "H" state to an "L" state is relatively long even for a load capacitance of 0.5 picofarads. By comparison, the time required to switch the Z output from the "L" level to the "H" level increases much more slowly with increasing load capacitances. The disadvantageous power consumption of this circuit is also demonstrated by the FIG. 3 simulation, which shows the constant pull-down current I.sub.EF required by the FIG. 2 ECL circuit.
The fact that the switching time from an "H" to an "L" (t.sub.pHL) is markedly slower than the switching time from an "L" to an "H" (t.sub.pLH) diminishes the overall performance of LSI circuits which use this type of ECL circuit. Slow and asymmetric switching times can cause an erroneous operation of the circuit due to signal skew (signal drift) or because of a racing condition in which the sequence of switching becomes reversed for competing signals. Furthermore, the heat generated by the large power consumption reduces the reliability of the ECL integrated circuit.
It is accordingly an object of the present invention to provide a circuit for ECL applications that achieves symmetric, fast switching times at low levels of power consumption.